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Learning Verilog on the Digilent Nexys2

For Christmas this year, I got a Digilent Nexys2 board.  My intention was to run this open source logic analyzer, to help improve my PS/2 keylogger.

I found the costs to be comparable to many of the low end logic analyzers on the market today, but the board itself has so much more potential, especially if you get the 1,200,000 gates version.  To get the logic analyzer to run, I simply needed to change the ucf file of the “Spartan 3E: Experimental Version for New Spartan 3E Starter Kit – Source (2007-03-08)” port. The RLE didn’t work for me, but it works great without it.

UCF for NEXYS2 and SUMP Logic Analyzer

I’ve played around with the board when I’ve had time, and it’s a lot of fun.  I started to do the tutorials on verilog.com – but I find I learn best hands on first, and then go back and look at specifics when I’ve got a good base.  When I came across these books, I was very excited and ordered them.  The neat thing is that the Basys book’s examples work perfectly on the Nexys2 board. They are geared to be very hands-on – which at this stage of the game is something that I think will work well for me.

I’ve already done a course that included most of the digital logic theory, so I didn’t have much of a learning curve when it came to those concepts, and once I started getting into the more complex circuits (starting at chapter 5), I was able to begin sinking my teeth in.

I downloaded Icarus, and GTKWave, and wrote my first test bench, to test the Verilog waters – and it went well.  I am looking forward to working through these books, and producing a FORTH computer by the end.

  1. compwiz
    February 8th, 2010 at 00:02 | #1

    I have a Nexys 2 board and have been having trouble getting the logic analyzer to work. Could you post the user constraints file or list any modifications to get it to work on the board?

  2. February 8th, 2010 at 08:56 | #2

    @compwiz
    Ensure you have downloaded the “Spartan 3E: Experimental Version for New Spartan 3E Starter Kit – Source (2007-03-08)” version, as it includes the BRAM.

    I’ve added the .ucf I was using to the post.

    Also, be aware that what you are sampling needs to be at 3.3v (say if your circuit is running at 5v). You may need to do a voltage conversion first.

  3. compwiz
    February 8th, 2010 at 11:51 | #3

    @Derek
    Thanks, I almost had the same exact modifications in the .ucf file just as you, but it still doesn’t work. Could you also post the .bit file?

    The LEDs seem to indicate that the board is working, the the rx LED seems to dim a little when data is being sent, but the Nexys 2 won’t communicate back with the computer.

  4. February 8th, 2010 at 12:14 | #4

    @compwiz
    I found enabling the RLE would greatly increase the sampling time. The logic analyzer will sample until the sample size is full, and only then does it communicate back to the host.

    I also found the RLE didn’t work, or produced garbage. Try:

    – turning off the RLE
    – reducing sample size

    Let me know if this helps.

    I am hesitant to post the .bit file because I forgot whether it was for running in flash, or programming directly, and I’m not sure what state it is in.

  5. compwiz
    February 8th, 2010 at 14:52 | #5

    @Derek
    I thought in order to initiate the sampling you needed to get the client to communicate with the board? I keep getting an Device Id 0x0 error.

    But if you need the sample size to be full in order for it to communicate, an LED will light up when it’s full?

    Also, is RLE turned on by default in the “Spartan 3E Starter Kit Port”? Is there a flag to turn it off? I don’t really understand the VHDL code. I program in Verilog.

    And lastly, I just need this logic analyzer to work so I could analyze the signals from another .bit file (designed for a Nexys 2 board) I lost the code for. If I can’t get the logic analyzer to work, could I email you my .bit file and have you analyze it for me?

  6. February 8th, 2010 at 15:47 | #6

    @compwiz
    You are right, you need to first be able to communicate with the board. I thought from your above comments that you were able to communicate to the board.

    I believe the .ucf is set for a null-modem cable. Try flipping the serial rx/tx pins, and recompiling, in case you have a straight-through serial cable. Also, I found the baud settings a little finicky, so play around with them first.

    The RLE should be disabled in the client software. There’s a check-box somewhere.

    I have no idea how I would analyze the signals from a .bit file with a piece of hardware. I only have one NEXYS2 board.

  7. compwiz
    February 8th, 2010 at 18:33 | #7

    @Derek
    Xilinx ISE wont let me switch the serial rx/tx pins unfortunately. It says the tx pin is only an output pin. So I tried switching the wires manuals and it still didn’t work.

    I have a feeling it might have something to do with my compiler. It gave 43 warnings, a couple of them having to do txBuffer.

  8. shuffle2
    November 21st, 2010 at 02:19 | #8

    Thanks for the post, just about to get a Nexys2 for another project – I wasn’t even aware that a logic analyzer existed for the platform, excellent :)

  9. solarwind
    September 30th, 2011 at 12:54 | #9

    I’m not able to get this to compile. I downloaded the package “Spartan 3E: Experimental Version for New Spartan 3E Starter Kit – Source (2007-03-08)”, as well as your UCF file, threw in the UCF file, removed the la-S3ESK.ucf file, and made it into a project. I get compile errors.

  10. October 2nd, 2011 at 20:32 | #10

    @solarwind
    What version of ISE are you using? I believe I was using ISE 10.

    Also, “I get compile errors” isn’t a very good description of the problem you are having. Providing more detail may help.

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